In the development of integrated semiconductor circuits the miniaturization of component dimensions represents an important development, in order to increase the number of integrated circuits on a semiconductor wafer and thus to reduce the production costs per integrated circuit. By way of example, a reduction of an exposure wavelength of the photolithography integrated into the process sequence makes it possible to shrink a minimum feature size such as e.g., a gate length or a width of interconnects. Consequently, the dimensions of an individual memory cell in a memory cell array can be reduced, which is linked with an increase in the memory density and a decrease in the production costs per memory bit.
With increasing structure miniaturization, stringent requirements are made of isolation arrangements such as e.g., STI (Shallow Trench Isolation) and spacers, since the isolation arrangements become thinner and thinner upon structure miniaturization and are nevertheless intended to ensure electrical isolation between semiconductor regions at different potentials.
For these and other reasons, there is a need for the present invention.